This disclosure is directed to computers and computer applications for managing power in a 3D chip stack and more particularly to computer-implemented methods and systems for power aware scheduling of requests in a 3D chip stack.
As future chip stacking technology advances, this will lead to a greater number of layers in a 3D stack. As the number of layers increases from today's 4 to 10 towards 40 or more, it will become increasingly hard to deliver power to all the layers. Issues will include voltage droop due to the numerous logic blocks powered by the same subset of Through-Silicon-Vias (TSVs). The TSVs will have insufficient power to handle all the memory requests for a large number of stacks. The above issue is yet to be encountered by current 3D chip designs as most stacks are limited to 3 to 8 layers. There is currently no solution to this critical issue for managing power.